The present invention relates to field effect transistors, and more specifically, to nanowire field effect transistors that have different wire thicknesses and different gate oxide thicknesses.
In typical complementary metal oxide semiconductor (CMOS) technologies, there usually are at two sets of devices. One set of devices forms the core logic high-performance devices and usually has a 1.0V operation voltage, or lower. The other set is optimized for interfacing to off chip devices and typically is optimized for 1.5V, or higher. This optimization drives a process that typically involves growing a thick dielectric everywhere, using lithography and a mask and a wet etch to remove the thick dielectric from some regions, and then growing a thinner dielectric in those regions. The high voltage devices are populated on thick dielectric regions and low voltage devices are built on the thin dielectric region. This process gives two distinct gate dielectrics and the two device types are then optimized around this structure. The negatives of this approach are that it requires an extra lithography and etch sequence, and any defects in the mask protecting the thick dielectric will directly translate into a yield loss for these devices.